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SOC VerIFICATION

RISC-V is an open-standard instruction set architecture. It has been gaining popularity because of its opern-source licensing. Several companies and research organizations are developing processors and SOCs based on the RISC-V architecture. We have inhouse expertise to help with your RISC-V based SOC projects.

Our SOC verification services include

Setup of a complete SOC verification flow including
- Hardware
- Software
Creating and integrating Verification IPs for the peripheral ports
Creating Hardware Abstraction Layer APIs
Setting up compiler tool chain for your SOC
Setting tup coverage collectors
Creating hardware-software interaction tests

Sample Project:
Verification of a RISC-V based SOC

RISC-V refers to an open source instruction set architecture developed at UC Berkeley. This ISA is gaining popularity and many teams around the world are designing processors and SOCs based on the RISC-V ISA. In this project we have implemented a complete verification framework for a RISC-V based SOC. This framework is designed in UVM and incorporates several VIPs for the peripherals. We have developed several tests to exercise the entire SOC. Each test contains two parts a "C"-based poriion, which provides the instructions for the CP,U and the UVM portion which manages the external stimuli
For more information refer to our publication

Verification of the PULPino SOC platform using UVM

RISC-V Woirkshop (2018) Chennai India,

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SOC VerIFICATION

Our SOC verification services include

Sample Project: Verification of a RISC-V based SOC

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info@verikwest.com

Sample Project:
Verification of a RISC-V based SOC